Datasheet

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
www.ti.com SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013
6 Electrical Specifications
6.1 Absolute Maximum Ratings
(1) (2)
Supply voltage range, V
DDIO
(I/O and Flash) with respect to V
SS
–0.3 V to 4.6 V
Supply voltage range, V
DD
with respect to V
SS
–0.3 V to 2.5 V
Analog voltage range, V
DDA
with respect to V
SSA
–0.3 V to 4.6 V
Input voltage range, V
IN
(3.3 V) –0.3 V to 4.6 V
Output voltage range, V
O
–0.3 V to 4.6 V
Input clamp current, I
IK
(V
IN
< 0 or V
IN
> V
DDIO
)
(3)
±20 mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
DDIO
) ±20 mA
Junction temperature range, T
J
(4)
–40°C to 150°C
Storage temperature range, T
stg
(4)
–65°C to 150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to V
SS
, unless otherwise noted.
(3) Continuous clamp current per pin is ± 2 mA.
(4) Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for
TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963).
6.2 Recommended Operating Conditions
MIN NOM MAX UNIT
Device supply voltage, I/O, V
DDIO
(1)(2)
2.97 3.3 3.63 V
Device supply voltage CPU, V
DD
(When internal 1.71 1.8 1.995
V
VREG is disabled and 1.8 V is supplied externally)
Supply ground, V
SS
0 V
Analog supply voltage, V
DDA
(1)
2.97 3.3 3.63 V
Analog ground, V
SSA
0 V
Device clock frequency (system clock) 28020, 28021, 280200 2 40
28022, 28023 2 50 MHz
28026, 28027 2 60
High-level input voltage, V
IH
(3.3 V) 2 V
DDIO
+ 0.3 V
Low-level input voltage, V
IL
(3.3 V) V
SS
– 0.3 0.8 V
High-level output source current, V
OH
= V
OH(MIN)
, I
OH
All GPIO/AIO pins –4 mA
Group 2
(3)
–8 mA
Low-level output sink current, V
OL
= V
OL(MAX)
, I
OL
All GPIO/AIO pins 4 mA
Group 2
(3)
8 mA
Junction temperature, T
J
(4)
T version –40 105
S version –40 125
°C
Q version –40 125
(Q100 Qualification)
(1) V
DDIO
and V
DDA
should be maintained within ~0.3 V of each other.
(2) A tolerance of ± 10% may be used for V
DDIO
if the BOR is not used. See the TMS320F28027, TMS320F28026, TMS320F28023,
TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200, TMS320F280270, TMS320F280260, TMS320F280230,
TMS320F280220 Piccolo MCU Silicon Errata (literature number SPRZ292) for more information. V
DDIO
tolerance is ±5% if the BOR is
enabled.
(3) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO19, GPIO28, GPIO29, GPIO36, GPIO37
(4) T
A
(Ambient temperature) is product- and application-dependent and can go up to the specified T
J
max of the device. See Section 6.5,
Thermal Design Considerations.
Copyright © 2008–2013, Texas Instruments Incorporated Electrical Specifications 79
Submit Documentation Feedback
Product Folder Links: TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021
TMS320F28020 TMS320F280200