Datasheet

GPxDAT (read)
Input
Qualification
GPxMUX1/2
HighImpedance
OutputControl
GPIOxpin
XRS
0=Input,1=Output
LowP ower
ModesBlock
GPxDIR(latch)
Peripheral2Input
Peripheral3Input
Peripheral1Output
Peripheral2Output
Peripheral3Output
Peripheral1OutputEnable
Peripheral2OutputEnable
Peripheral3OutputEnable
00
01
10
11
00
01
10
11
00
01
10
11
GPxCTRL
Peripheral1Input
N/C
GPxPUD
LPMCR0
Internal
Pullup
GPIOLMPSEL
GPxQSEL1/2
GPxSET
GPxDAT (latch)
GPxCLEAR
GPxTOGGLE
=DefaultatReset
PIE
ExternalInterrupt
MUX
Asynchronous
path
Asynchronouspath
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013 www.ti.com
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the
TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide (literature number
SPRUFN3) for pin-specific variations.
Figure 4-12. GPIO Multiplexing
74 Peripherals Copyright © 2008–2013, Texas Instruments Incorporated
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Product Folder Links: TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021
TMS320F28020 TMS320F280200