Datasheet

TSCTR
(counter−32bit)
RST
CAP1
(APRDactive)
LD
CAP2
(ACMPactive)
LD
CAP3
(APRDshadow)
LD
CAP4
(ACMPshadow)
LD
Continuous/
Oneshot
CaptureControl
LD1
LD2
LD3
LD4
32
32
PRD[0−31]
CMP[0−31]
CTR[0−31]
eCAPx
Interrupt
Trigger
and
Flag
control
toPIE
CTR=CMP
32
32
32
32
32
ACMP
shadow
Event
Pre-scale
CTRPHS
(phaseregister−32bit)
SYNCOut
SYNCIn
Event
qualifier
Polarity
select
Polarity
select
Polarity
select
Polarity
select
CTR=PRD
CTR_OVF
4
PWM
compare
logic
CTR[0−31]
PRD[0−31]
CMP[0−31]
CTR=CMP
CTR=PRD
CTR_OVF
OVF
APWMmode
Delta−mode
SYNC
4
Captureevents
CEVT[1:4]
APRD
shadow
32
32
MODESELECT
TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
www.ti.com SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013
4.7 Enhanced Capture Module (eCAP1)
The device contains an enhanced capture (eCAP) module. Figure 4-10 shows a functional block diagram
of a module.
Figure 4-10. eCAP Functional Block Diagram
The eCAP module is clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for
low power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
Copyright © 2008–2013, Texas Instruments Incorporated Peripherals 67
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