Datasheet

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013 www.ti.com
The SCI port operation is configured and controlled by the registers listed in Table 4-5.
Table 4-5. SCI-A Registers
(1)
EALLOW
NAME ADDRESS SIZE (x16) DESCRIPTION
PROTECTED
SCICCRA 0x7050 1 No SCI-A Communications Control Register
SCICTL1A 0x7051 1 No SCI-A Control Register 1
SCIHBAUDA 0x7052 1 No SCI-A Baud Register, High Bits
SCILBAUDA 0x7053 1 No SCI-A Baud Register, Low Bits
SCICTL2A 0x7054 1 No SCI-A Control Register 2
SCIRXSTA 0x7055 1 No SCI-A Receive Status Register
SCIRXEMUA 0x7056 1 No SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA 0x7057 1 No SCI-A Receive Data Buffer Register
SCITXBUFA 0x7059 1 No SCI-A Transmit Data Buffer Register
SCIFFTXA
(2)
0x705A 1 No SCI-A FIFO Transmit Register
SCIFFRXA
(2)
0x705B 1 No SCI-A FIFO Receive Register
SCIFFCTA
(2)
0x705C 1 No SCI-A FIFO Control Register
SCIPRIA 0x705F 1 No SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
58 Peripherals Copyright © 2008–2013, Texas Instruments Incorporated
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