Datasheet

S
SPICTL.0
SPIINTFLAG
SPIINT
ENA
SPISTS.6
S
Clock
Polarity
Talk
LSPCLK
SPIBitRate
StateControl
SPIRXBUF
BufferRegister
Clock
Phase
Receiver
OverrunFlag
SPICTL.4
Overrun
INTENA
SPICCR.3-0
SPIBRR.6-0
SPICCR.6
SPICTL.3
SPIDAT.15-0
SPICTL.1
M
S
M
Master/Slave
SPISTS.7
SPIDAT
DataRegister
M
S
SPICTL.2
SPIChar
SPISIMO
SPISOMI
SPICLK
SW2
S
M
M
S
SW3
ToCPU
M
SW1
SPITXBUF
BufferRegister
RXFIFO_0
RXFIFO_1
-----
RXFIFO_3
TXFIFORegisters
TXFIFO_0
TXFIFO_1
-----
TXFIFO_3
RXFIFORegisters
16
16
16
TXInterrupt
Logic
RXInterrupt
Logic
SPIINT
SPITX
SPIFFOVF
FLAG
SPIFFRX.15
TXFIFOInterrupt
RXFIFOInterrupt
SPIRXBUF
SPITXBUF
SPIFFTX.14
SPIFFENA
SPISTE
16
0
12
3
0
12
3
4
5
6
TW
SPIPRI.0
TW
TW
TRIWIRE
TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013 www.ti.com
Figure 4-5 is a block diagram of the SPI in slave mode.
A. SPISTE is driven low by the master for a slave device.
Figure 4-5. SPI Module Block Diagram (Slave Mode)
56 Peripherals Copyright © 2008–2013, Texas Instruments Incorporated
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Product Folder Links: TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021
TMS320F28020 TMS320F280200