Datasheet

38-Pin
48-Pin
VDDA
VDDA
VREFLO
Tied To
VSSA
VREFLO
Tied To
VSSA
VREFHI
Tied To
A0
VREFHI
Tied To
A0
A1
A2
A2
A3
A4
A4
A6
A6
A7
B1
B2
B2
B3
B4
B4
B6
B6
B7
(3.3 V) VDDA
(Agnd) VSSA
VREFLO
Diff
Interface Reference
Comp1
VREFHI
A0
B0
AIO2
AIO10
A1
B1
10-Bit
DAC
A2
B2
COMP1OUT
A3
B3
Comp2
(See Note A)
AIO4
AIO12
10-Bit
DAC
A4
B4
COMP2OUT
ADC
B5
AIO6
AIO14
A6
B6
A7
B7
Simultaneous Sampling Channels
Signal Pinout
A5
Temperature Sensor
TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013 www.ti.com
4 Peripherals
4.1 Analog Block
A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on F280x/F2833x.
The ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the
timing control of start of conversions. Figure 4-1 shows the interaction of the analog module with the rest
of the F2802x system.
A. Comparator 2 is only available on the 48-pin PT package.
Figure 4-1. Analog Pin Configurations
48 Peripherals Copyright © 2008–2013, Texas Instruments Incorporated
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TMS320F28020 TMS320F280200