Datasheet

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
www.ti.com SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013
3.3 Register Map
The devices contain three peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.
See Table 3-8.
Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See
Table 3-9.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See
Table 3-10.
Table 3-8. Peripheral Frame 0 Registers
(1)
NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
(2)
Device Emulation Registers 0x00 0880 – 0x00 0984 261 Yes
System Power Control Registers 0x00 0985 – 0x00 0987 3 Yes
FLASH Registers
(3)
0x00 0A80 – 0x00 0ADF 96 Yes
Code Security Module Registers 0x00 0AE0 – 0x00 0AEF 16 Yes
ADC registers 0x00 0B00 – 0x00 0B0F 16 No
(0 wait read only)
CPU–TIMER0/1/2 Registers 0x00 0C00 – 0x00 0C3F 64 No
PIE Registers 0x00 0CE0 – 0x00 0CFF 32 No
PIE Vector Table 0x00 0D00 – 0x00 0DFF 256 No
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
Table 3-9. Peripheral Frame 1 Registers
NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
Comparator 1 registers 0x00 6400 – 0x00 641F 32
(1)
Comparator 2 registers 0x00 6420 – 0x00 643F 32
(1)
ePWM1 + HRPWM1 registers 0x00 6800 – 0x00 683F 64
(1)
ePWM2 + HRPWM2 registers 0x00 6840 – 0x00 687F 64
(1)
ePWM3 + HRPWM3 registers 0x00 6880 – 0x00 68BF 64
(1)
ePWM4 + HRPWM4 registers 0x00 68C0 – 0x00 68FF 64
(1)
eCAP1 registers 0x00 6A00 – 0x00 6A1F 32 No
GPIO registers 0x00 6F80 – 0x00 6FFF 128
(1)
(1) Some registers are EALLOW protected. See the module reference guide for more information.
Table 3-10. Peripheral Frame 2 Registers
NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
System Control Registers 0x00 7010 – 0x00 702F 32 Yes
SPI-A Registers 0x00 7040 – 0x00 704F 16 No
SCI-A Registers 0x00 7050 – 0x00 705F 16 No
NMI Watchdog Interrupt Registers 0x00 7060 – 0x00 706F 16 Yes
External Interrupt Registers 0x00 7070 – 0x00 707F 16 Yes
ADC Registers 0x00 7100 – 0x00 717F 128
(1)
I2C-A Registers 0x00 7900 – 0x00 793F 64
(1)
(1) Some registers are EALLOW protected. See the module reference guide for more information.
Copyright © 2008–2013, Texas Instruments Incorporated Functional Overview 31
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