Datasheet

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
www.ti.com SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013
Disclaimer
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED
TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY
(EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN
ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO
TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR
THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT
AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS
CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY
OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,
BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR
INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.
3.2.10 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the F2802x, 33 of the possible 96 interrupts are
used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of
12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a
dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU
on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.
Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in
hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.
3.2.11 External Interrupts (XINT1–XINT3)
The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be
selected for negative, positive, or both negative and positive edge triggering and can also be
enabled/disabled. These interrupts also contain a 16-bit free running up counter, which is reset to zero
when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt.
There are no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept
inputs from GPIO0–GPIO31 pins.
3.2.12 Internal Zero Pin Oscillators, Oscillator, and PLL
The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a
crystal attached to the on-chip oscillator circuit (48-pin devices only). A PLL is provided supporting up to
12 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to
scale back on operating frequency if lower power operation is desired. Refer to Section 6, Electrical
Specifications, for timing details. The PLL block can be set in bypass mode.
3.2.13 Watchdog
Each device contains two watchdogs: CPU-Watchdog that monitors the core and NMI-Watchdog that is a
missing clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a
certain time frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog
can be disabled if necessary. The NMI-Watchdog engages only in case of a clock failure and can either
generate an interrupt or a device reset.
Copyright © 2008–2013, Texas Instruments Incorporated Functional Overview 27
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Product Folder Links: TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021
TMS320F28020 TMS320F280200