Datasheet

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
www.ti.com SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013
Table 6-47. Flash Parameters at 40-MHz SYSCLKOUT
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
I
DDP
(1)
V
DD
current consumption during Erase/Program cycle VREG 60 mA
disabled
I
DDIOP
(1)
V
DDIO
current consumption during Erase/Program cycle 60
I
DDIOP
(1)
V
DDIO
current consumption during Erase/Program cycle VREG enabled 100 mA
(1) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure V
MIN
on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during
flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed
during the programming process.
Table 6-48. Flash Program/Erase Time
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
Program Time 16-Bit Word 50 μs
8K Sector 250 ms
4K Sector 125 ms
Erase Time
(1)
8K Sector 2 s
4K Sector 2 s
(1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
Table 6-49. Flash/OTP Access Timing
PARAMETER MIN MAX UNIT
t
a(fp)
Paged Flash access time 40 ns
t
a(fr)
Random Flash access time 40 ns
t
a(OTP)
OTP access time 60 ns
Table 6-50. Flash Data Retention Duration
PARAMETER TEST CONDITIONS MIN MAX UNIT
t
retention
Data retention duration T
J
= 55°C 15 years
Table 6-51. Minimum Required Flash/OTP Wait-States at Different Frequencies
SYSCLKOUT SYSCLKOUT PAGE RANDOM OTP
(MHz) (ns) WAIT-STATE
(1)
WAIT-STATE
(1)
WAIT-STATE
60 16.67 2 2 3
55 18.18 2 2 3
50 20 1 1 2
45 22.22 1 1 2
40 25 1 1 2
35 28.57 1 1 2
30 33.33 1 1 1
25 40 0 1 1
(1) Random wait-state must be ≥ 1.
Copyright © 2008–2013, Texas Instruments Incorporated Electrical Specifications 121
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TMS320F28020 TMS320F280200