Datasheet

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013 www.ti.com
6.11.11 On-Chip Analog-to-Digital Converter
Table 6-38. ADC Electrical Characteristics
PARAMETER MIN TYP MAX UNIT
DC SPECIFICATIONS
Resolution 12 Bits
ADC clock 60-MHz device 0.001 60 MHz
Sample Window 28027/26/23/22 7 64 ADC
Clocks
28021/20/200 14 64
ACCURACY
INL (Integral nonlinearity) at ADC Clock ≤ 30 MHz
(1)
–4 4 LSB
DNL (Differential nonlinearity) at ADC Clock ≤ 30 MHz, –1 1 LSB
no missing codes
Offset error
(2)
Executing Device_Cal –20 0 20 LSB
function
Executing periodic self- –4 0 4
recalibration
(3)
Overall gain error with internal reference –60 60 LSB
Overall gain error with external reference –40 40 LSB
Channel-to-channel offset variation –4 4 LSB
Channel-to-channel gain variation –4 4 LSB
ADC temperature coefficient with internal reference –50 ppm/°C
ADC temperature coefficient with external reference –20 ppm/°C
V
REFLO
–100 µA
V
REFHI
100 µA
ANALOG INPUT
Analog input voltage with internal reference 0 3.3 V
Analog input voltage with external reference V
REFLO
V
REFHI
V
V
REFLO
input voltage
(4)
V
SSA
V
SSA
V
V
REFHI
input voltage
(5)
with V
REFLO
= V
SSA
1.98 V
DDA
V
Input capacitance 5 pF
Input leakage current ±5 μA
(1) INL will degrade when the ADC input voltage goes above V
DDA
.
(2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and V
REFHI
- V
REFLO
for external
reference.
(3) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be performed
as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset Calibration"
section of the TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator Reference Guide (literature number
SPRUGE5).
(4) V
REFLO
is always connected to V
SSA
.
(5) V
REFHI
must not exceed V
DDA
when using either internal or external reference modes. Since V
REFHI
is tied to ADCINA0, the input signal
on ADCINA0 must not exceed V
DDA
.
112 Electrical Specifications Copyright © 2008–2013, Texas Instruments Incorporated
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