Datasheet

20
15
SPISIMO
SPISOMI
SPICLK
(clockpolarity=1)
SPICLK
(clockpolarity=0)
SPISIMOdata
mustbevalid
SPISOMIdataIsvalid
19
16
14
13
12
SPISTE
(A)
TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
www.ti.com SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013
6.11.9 SPI Slave Mode Timing
Table 6-35 lists the slave mode external timing (clock phase = 0) and Table 6-36 (clock phase = 1).
Figure 6-22 and Figure 6-23 show the timing waveforms.
Table 6-35. SPI Slave Mode External Timing (Clock Phase = 0)
(1)(2)(3)(4)(5)
NO. MIN MAX UNIT
12 t
c(SPC)S
Cycle time, SPICLK 4t
c(LCO)
ns
13 t
w(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0) 0.5t
c(SPC)S
– 10 0.5t
c(SPC)S
ns
t
w(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1) 0.5t
c(SPC)S
– 10 0.5t
c(SPC)S
14 t
w(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0) 0.5t
c(SPC)S
– 10 0.5t
c(SPC)S
ns
t
w(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1) 0.5t
c(SPC)S
– 10 0.5t
c(SPC)S
15 t
d(SPCH-SOMI)S
Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) 21 ns
t
d(SPCL-SOMI)S
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 21
16 t
v(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) 0.75t
c(SPC)S
ns
t
v(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) 0.75t
c(SPC)S
19 t
su(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0) 26 ns
t
su(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 1) 26
20 t
v(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5t
c(SPC)S
– 10 ns
t
v(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5t
c(SPC)S
– 10
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) t
c(SPC)
= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(4) t
c(LCO)
= LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5t
c(SPC)
(minimum) before the valid SPI clock
edge and remain low for at least 0.5t
c(SPC)
after the receiving edge (SPICLK) of the last data bit.
Figure 6-22. SPI Slave Mode External Timing (Clock Phase = 0)
Copyright © 2008–2013, Texas Instruments Incorporated Electrical Specifications 109
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