Datasheet

DataValid
11
SPISOMI
SPISIMO
SPICLK
(clockpolarity=1)
SPICLK
(clockpolarity=0)
Masterindata
mustbevalid
MasteroutdataIsvalid
1
7
6
10
3
2
SPISTE
(A)
TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013 www.ti.com
A. In the master mode, SPISTE goes active 0.5t
c(SPC)
(minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5t
c(SPC)
after
the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-21. SPI Master Mode External Timing (Clock Phase = 1)
108 Electrical Specifications Copyright © 2008–2013, Texas Instruments Incorporated
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TMS320F28020 TMS320F280200