Datasheet

XINT1,XINT2,XINT3
t
w(INT)
InterruptVector
t
d(INT)
Addressbus
(internal)
TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
www.ti.com SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013
6.11.6 External Interrupt Timing
Table 6-30. External Interrupt Timing Requirements
(1)
TEST CONDITIONS MIN MAX UNIT
t
w(INT)
(2)
Pulse duration, INT input low/high Synchronous 1t
c(SCO)
cycles
With qualifier 1t
c(SCO)
+ t
w(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-16.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
Table 6-31. External Interrupt Switching Characteristics
(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
t
d(INT)
Delay time, INT low/high to interrupt-vector fetch t
w(IQSW)
+ 12t
c(SCO)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-16.
Figure 6-19. External Interrupt Timing
Copyright © 2008–2013, Texas Instruments Incorporated Electrical Specifications 103
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