Datasheet

PWM
(B)
TZ
(A)
SYSCLK
t
w(TZ)
t
d(TZ-PWM)HZ
TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
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SPRS523J NOVEMBER 2008REVISED OCTOBER 2013
6.11 Enhanced Control Peripherals
6.11.1 Enhanced Pulse Width Modulator (ePWM) Timing
PWM refers to PWM outputs on ePWM1–4. Table 6-23 shows the PWM timing requirements and Table 6-
24, switching characteristics.
Table 6-23. ePWM Timing Requirements
(1)
TEST CONDITIONS MIN MAX UNIT
t
w(SYCIN)
Sync input pulse width Asynchronous 2t
c(SCO)
cycles
Synchronous 2t
c(SCO)
cycles
With input qualifier 1t
c(SCO)
+ t
w(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-16.
Table 6-24. ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
t
w(PWM)
Pulse duration, PWMx output high/low 33.33 ns
t
w(SYNCOUT)
Sync output pulse width 8t
c(SCO)
cycles
t
d(PWM)tza
Delay time, trip input active to PWM forced high no pin load 25 ns
Delay time, trip input active to PWM forced low
t
d(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z 20 ns
6.11.2 Trip-Zone Input Timing
Table 6-25. Trip-Zone Input Timing Requirements
(1)
MIN MAX UNIT
t
w(TZ)
Pulse duration, TZx input low Asynchronous 2t
c(TBCLK)
cycles
Synchronous 2t
c(TBCLK)
cycles
With input qualifier 2t
c(TBCLK)
+ t
w(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-16.
A. TZ - TZ1, TZ2, TZ3
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-17. PWM Hi-Z Characteristics
Copyright © 2008–2013, Texas Instruments Incorporated Electrical Specifications 101
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