Video Port/VCXO Interpolated Control (VIC) Port User's Guide

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VDIN[19−12]
Cr Buffer (1280 bytes)
Cb Buffer (1280 bytes)
8
8
64
64
CRSRCA
CBSRCA
Y Buffer (2560 bytes)
VDIN[9−2]
8
64
Capture FIFO
YSRCA
Video Port FIFO
For Y/C video capture, the FIFO is configured as a single channel split into separate Y, Cb, and Cr buffers
with separate write pointers and read registers (YSRCA, CBSRCA, and CRSRCA). Figure 1-4 shows how
Y data is received on the VDIN[9-2] half of the bus and Cb/Cr data is received on the VDIN[19-12] half of
the bus and de-multiplexed into the Cb and Cr buffers.
Figure 1-4. Y/C Video Capture FIFO Configuration
22 Overview SPRUEM1 – May 2007
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