Video Port/VCXO Interpolated Control (VIC) Port User's Guide

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4.10 Displaying Video in BT.656 or Y/C Mode
Displaying Video in BT.656 or Y/C Mode
In order to display video in the BT.656 or Y/C format, the following steps are needed:
1. To use the desired Video Port, program the Pin Mux Register (PINMUX) appropriately to ensure that
the multiplexed pins work as Video Port Pins. Refer to the device-specific data manual for details about
PINMUX register.
2. Program the VPx_CTL Register appropriately to use the desired Video Port as a Display Port.
3. Set the PEREN bit in the video port peripheral control register (PCR).
4. Set the frame size in VDFRMSZ. Set the number of lines per frame (FRMHIGHT) and the number of
pixels per line (FRMWIDTH).
5. Set the horizontal blanking in VDHBLNK. Specify the frame pixel counter value where horizontal
blanking starts (HBLNKSTART) and pixel location where horizontal blanking stops (HBLNKSTOP).
6. Set the V bit timing for field 1 in VDVBIT1. Specify the line where the V bit is set (VBITSET1) and the
line where the V bit is cleared (VBITCLR1).
7. If external VBLNK signal is needed, set the VBLNK start for field 1 in VDVBLKS1. Specify the frame
line (VBLNKYSTART1) and frame pixel counter (VBLNKXSTART1) values for the pixel where VBLNK
goes active for field 1. Set the VBLNK end for field 1 in VDVBLKE1. Specify the frame line
(VBLNKYSTOP1) and frame pixel counter (VBLNKXSTOP1) values for the pixel where VBLNK goes
inactive for field 1.
8. Set the V bit timing for field 2 in VDVBIT2. Specify the line where the V bit is set (VBITSET2) and the
line where the V bit is cleared (VBITCLR2).
9. If external VBLNK signal is needed, set the VBLNK start for field 2 in VDVBLKS2. Specify the frame
line (VBLNKYSTART2) and frame pixel counter (VBLNKXSTART2) values for the pixel where VBLNK
goes active for field 2. Set the VBLNK end for field 2 in VDVBLKE2. Specify the frame line
(VBLNKYSTOP2) and frame pixel counter (VBLNKXSTOP2) values for the pixel where VBLNK goes
inactive for field 2.
10. Set VDIMGSZ n. Adjust the displayed image size by setting the HSIZE and VSIZE bits.
11. Set VDIMOFF. Adjust the displayed image offset within the active video area (by setting HOFFSET
and VOFFSET).
12. Set the F bit timing in VDFBIT. Specify the line where the F bit is cleared (FBITCLR) and the line
where the F bit is set (FBITSET).
13. If external FLD output is required, set the video display field 1 timing. Specify the line and pixel where
FLD goes inactive (VDFLDT1). Set the video display field 2 timing. Specify the line and pixel where
FLD goes active (VDFLDT2).
14. Set VDCLIP. Default values for video clipping are 16 for the lower clipping, 235 for the higher clipping
of the Y values, and 240 for the higher clipping of the Cb and Cr values.
15. Configure an EDMA to move data from the Y buffer in the DSP memory to YDSTA (memory-mapped
Y display FIFO). The transfers should be triggered by the YEVT.
16. Configure an EDMA to move data from the Cb buffer in the DSP memory to CBDST
(memory-mapped Cb display FIFO). The transfers should be triggered by the CbEVT. The size of the
transfers should be set to 1/2 the Y transfer size.
17. Configure an EDMA to move data from the Cr buffer in the DSP memory to CRDST (memory-mapped
Cr display FIFO). The transfers should be triggered by the CrEVT. The size of the transfers should be
set to 1/2 the Y transfer size.
18. Set DISPEVT1 and DISPEVT2 bits in VDDISPEVT. Event count is total double words per field divided
by total double words per Y EDMA transfer size.
19. Write to VPIE to enable under-run (DUND) and display complete (DCMP) interrupts, if desired.
20. Write to VDTHRLD to set the display FIFO threshold (VDTHRLD bits).
21. Write to VDCTL to:
• Set display mode (DMODE = 00x for BT.656 output, 10x for Y/C output).
• Set desired field/frame operation (CON, FRAME, DF1, DF2 bits).
• Select control outputs (VCTL1S, VCTL2S, VCTL3S bits) or external sync inputs (HXS, VXS, FXS
bits).
• Enable scaling (SCALE and RESMPL bits), if desired and in 8-bit mode.
• Set VDEN bit to enable the display.
SPRUEM1 – May 2007 Video Display Port 119
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