Video Port/VCXO Interpolated Control (VIC) Port User's Guide

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4.9.3 Y/C Progressive Display Example
Display Timing Examples
This section shows an example of progressive display operation. The output format follows SMPTE
296M-2001 specifications for a 1280 x 720/60 system. The example is for a 1264 x 716 progressive output
image.
The horizontal output timing is shown in Figure 4-29 . This diagram assumes that there is a two VCLK
pipeline delay between the internal counter changing and the output on external pins. The actual delay
can be longer or shorter as long as it is consistent within any display mode. The SMPTE 296M 60-Hz
active line is 1650-pixels wide. Figure 4-29 shows the 1264-pixel image window centered in the screen
that results in an IMGHOFF x of 8 pixels.
The HBLNK and HSYNC signals are shown as they would be output for active-low operation. Note that
only one of the two signals is actually available externally. The HBLNK inactive edge occurs either on
sample 1646 coincident with the start of SAV or on sample 0 (after SAV) if the HBDLA bit is set. For true
SMPTE 296M operation, neither HBLNK nor HSYNC would be used.
The IPCOUNT operation follows the description in Section 4.1.2 . IPCOUNT resets to 0 at the first
displayed pixel (FPCOUNT = IMGHOFF x) and stops counting at the last displayed pixel (IPCOUNT =
IMGHSIZE x). The operation during non-display time is not a requirement, it could continue counting until
the next FPCOUNT = IMGHOFF x point or it could reset immediately after IMGHSIZE x or when FPCOUNT
is reset.
VDOUT shows the output data and switching between EAV, Blanking Data, SAV, Default Data, and FIFO
Data. It is assumed that the DVEN bit in VDCTL is set to enable the default output.
116 Video Display Port SPRUEM1 – May 2007
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