Output (MDIO) Module User's Guide

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5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)

5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)

Ethernet Media Access Controller (EMAC) Registers

The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 59 and described in

Table 58 .

Figure 59. MAC Interrupt Mask Set Register (MACINTMASKSET)

31 16

Reserved

R-0

15 2 1 0

Reserved HOSTMASK STATMASK

R-0 R/W1S-0 R/W1S-0

LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; - n = value after reset

Table 58. MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions

Bit Field Value Description

31-2 Reserved 0 Reserved

1 HOSTMASK 0-1 Host error interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.

0 STATMASK 0-1 Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.

The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Figure 60 and described in

Table 59 .

Figure 60. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)

31 16

Reserved

R-0

15 2 1 0

Reserved HOSTMASK STATMASK

R-0 R/W1C-0 R/W1C-0

LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; - n = value after reset

Table 59. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions

Bit Field Value Description

31-2 Reserved 0 Reserved

1 HOSTMASK 0-1 Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

0 STATMASK 0-1 Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

SPRUEQ6 – December 2007 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 101

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