TMS320DM644x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller User's Guide

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4.2 MMC Memory Clock Control Register (MMCCLK)
Registers
The MMC memory clock control register (MMCCLK) is used to:
• Select whether the CLK pin is enabled or disabled (CLKEN bit).
• Select how much the function clock is divided-down to produce the memory clock (CLKRT bits). When
the CLK pin is enabled, the MMC controller drives the memory clock on this pin to control the timing of
communications with attached memory cards. For more details about clock generation, see
Section 2.1 .
The MMC memory clock control register (MMCCLK) is shown in Figure 19 and described in Table 7 .
Figure 19. MMC Memory Clock Control Register (MMCCLK)
31 16
Reserved
R-0
15 9 8 7 0
Reserved CLKEN CLKRT
R-0 R/W-0 R/W–FFh
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 7. MMC Memory Clock Control Register (MMCCLK) Field Descriptions
Bit Field Value Description
31-9 Reserved 0 Reserved
8 CLKEN CLK pin enable.
0 CLK pin is disabled and fixed low.
1 The CLK pin is enabled; it shows the memory clock signal.
7-0 CLKRT 0–FFh Clock rate. Use this field to set the divide-down value for the memory clock. The function clock is
divided down as follows to produce the memory clock:
memory clock frequency = function clock frequency/(2 × (CLKRT + 1) )
Multimedia Card (MMC)/Secure Digital (SD) Card Controller42 SPRUE30B – September 2006
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