TMS320DM644x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller User's Guide

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ARM/EDMA reads/writes
Write Read
FIFO
8−bit x 32
(256−bit)
FIFO
EDMA event
128 or 256 bit
128 or 256 bit
EDMA event
EDMA event
the end of a
transfer
Pointer increment
or decrease
Pointer increment
or decrease
FIFO
16−bit DXR 16−bit DRR
16−bit DXR
shifter
16−bit DRR
shifter
DXR DRR
EDMA
request
is created
Transmission of data
Step 1: Set FIFO reset
Step 2: Set FIFO direction
Step 4: CPU driven transaction:
Fill the FIFO by writing to
MMCDXR (only first time)
Step 5: EDMA send xmit data
Step 6: If DXR ready is active,
FIFO −> 16−bit DXR
Reception of data
Step 3:
Step 2:
Step 1: Set FIFO reset
Set FIFO direction
If DRR ready is active,
16−bit DRR −> FIFO
Step 6: EDMA read reception data
Step 4: EDMA driven transaction
Step 5: DRRDYINT interrupt occur
Step 3: EDMA driven transaction
or every 128 or 256−bits
transmitted and DXRDYINT
interrupt is generated
when FIFO every 128 or
256−bits of data received
by FIFO
Peripheral Architecture
A high-level operational description is as follows:
• Data is written to the FIFO through the MMC data transmit register (MMCDXR). Data is read from the
FIFO through the MMC data receive register (MMCDRR). This is true for both the CPU and EDMA
driven transactions; however, for the EDMA transaction, the EDMA access to the FIFO is transparent.
• The ACCWD bits in the MMC FIFO control register (MMCFIFOCTL) determines the behavior of the
FIFO full (FIFOFUL) and FIFO empty (FIFOEMP) status flags in the MMC status register 1 (MMCST1):
– If ACCWD = 00b:
• FIFO full is active when the write pointer + 4 > read pointer
• FIFO empty is active when the write pointer - 4 < read pointer
– If ACCWD = 01b:
• FIFO full is active when the write pointer + 3 > read pointer
• FIFO empty is active when the write pointer - 3 < read pointer
– If ACCWD = 10b:
• FIFO full is active when the write pointer + 2 > read pointer
• FIFO empty is active when the write pointer - 2 < read pointer
– If ACCWD = 11b:
• FIFO full is active when the write pointer + 1 > read pointer
• FIFO empty is active when the write pointer - 1 < read pointer
Figure 7. FIFO Operation Diagram
Multimedia Card (MMC)/Secure Digital (SD) Card Controller16 SPRUE30B – September 2006
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