DSP Subsystem Reference Guide

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9.4 3.3 V I/O Power-Down Control
9.5 Peripheral Status and Control
9.5.1 Timer Control
9.5.2 VPSS Clock and DAC Control
9.5.3 DDR2 VTP Control
9.5.4 HPI Control
3.3 V I/O Power-Down Control
The VDD3P3V_PWDN register controls power to the 3.3 V I/O cells. Some 3.3 V I/Os default to power
down for power saving. See device-specific data manual for the description of the VDD3P3V_PWDN
register.
Several of the DM643x DMP peripheral modules require additional system-level control logic. Those
registers are discussed in this section.
The Timer control register (TIMERCTL) provides additional control for Timer 0 and Timer 2 (Watchdog
Timer). See the device-specific data manual for details on this register.
Clocks for the video processing subsystem (VPSS) are controlled via the VPSS clock control register
(VPSS_CLKCTL). See the device-specific data manual for details on this register.
The DDR2 VTP Enable Register (DDRVTPER) is used along with other registers in the VTP IO buffer
calibration process for the DDR2 memory controller. See the device-specific data manual for the location
of this register. See the TMS320DM643x DMP DDR2 Memory Controller User's Guide (SPRU986 ) for
more details on the VTP IO buffer calibration process.
The HPI Control Register (HPICTL) controls the host burst write time-out value for HPI operation. See the
device-specific data manual for details on this register.
SPRU978E – March 2008 System Module 87
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