DSP Subsystem Reference Guide

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6.7.3 Module Error Pending Register 1 (MERRPR1)
6.7.4 Module Error Clear Register 1 (MERRCR1)
PSC Registers
The module error pending register 1 (MERRPR1) is shown in Figure 6-4 and described in Table 6-8 . Only
the C64x+ CPU (module 39) can have an error condition, as it is the only module with IcePick support.
See Section 6.5 for more information.
Figure 6-4. Module Error Pending Register 1 (MERRPR1)
31 16
Reserved
R-0
15 8 7 6 0
Reserved M[39] Reserved
R-0 R-0 R-0
LEGEND: R = Read only; - n = value after reset
Table 6-8. Module Error Pending Register 1 (MERRPR1) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7 M[39] Module interrupt status bit for module 39 (C64x+ CPU).
0 Module 39 does not have an error condition.
1 Module 39 has an error condition. See the module status 39 register (MDSTAT39) for the exact error
condition.
6-0 Reserved 0 Reserved
The module error clear register 1 (MERRCR1) is shown in Figure 6-5 and described in Table 6-9 . Only the
C64x+ CPU (module 39) can have an error condition, as it is the only module with IcePick support.
Figure 6-5. Module Error Clear Register 1 (MERRCR1)
31 16
Reserved
R-0
15 8 7 6 0
Reserved M[39] Reserved
R-0 W-0 R-0
LEGEND: R = Read only; W = Write only; - n = value after reset
Table 6-9. Module Error Clear Register 1 (MERRCR1) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7 M[39] Clears the interrupt status bits set in the corresponding module error pending register 1 (MERRPR1)
and the module status 39 register (MDSTAT39). This pertains to module 39.
0 A write of 0 has no effect.
1 Clears module interrupt status bits: the M[39] bit in MERRPR1, the EMURST bit and the EMUIHB bit in
MDSTAT39.
6-0 Reserved 0 Reserved
Power and Sleep Controller70 SPRU978E – March 2008
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