DSP Subsystem Reference Guide

List of Figures
1-1 TMS320DM643x DMP Block Diagram .................................................................................. 12
2-1 TMS320C64x+ Megamodule Block Diagram ........................................................................... 17
2-2 C64x+ Cache Memory Architecture ...................................................................................... 19
4-1 Overall Clocking Diagram ................................................................................................. 31
4-2 VPBE/DAC Clocking ....................................................................................................... 35
5-1 PLL1 Structure in the TMS320DM643x DMP .......................................................................... 39
5-2 PLL2 Structure in the TMS320DM643x DMP .......................................................................... 43
5-3 Peripheral ID Register (PID) .............................................................................................. 49
5-4 Reset Type Status Register (RSTYPE) ................................................................................. 49
5-5 PLL Control Register (PLLCTL) .......................................................................................... 50
5-6 PLL Multiplier Control Register (PLLM) ................................................................................. 51
5-7 PLL Controller Divider 1 Register (PLLDIV1) ........................................................................... 51
5-8 PLL Controller Divider 2 Register (PLLDIV2) .......................................................................... 52
5-9 PLL Controller Divider 3 Register (PLLDIV3) .......................................................................... 52
5-10 Oscillator Divider 1 Register (OSCDIV1) ................................................................................ 53
5-11 Bypass Divider Register (BPDIV) ........................................................................................ 54
5-12 PLL Controller Command Register (PLLCMD) ......................................................................... 55
5-13 PLL Controller Status Register (PLLSTAT) ............................................................................. 55
5-14 PLL Controller Clock Align Control Register (ALNCTL) ............................................................... 56
5-15 PLLDIV Ratio Change Status Register (DCHANGE) .................................................................. 57
5-16 Clock Enable Control Register (CKEN) ................................................................................. 58
5-17 Clock Status Register (CKSTAT) ........................................................................................ 59
5-18 SYSCLK Status Register (SYSTAT) ..................................................................................... 60
6-1 Power and Sleep Controller (PSC) Integration ......................................................................... 62
6-2 Peripheral Revision and Class Information Register (PID) ........................................................... 69
6-3 Interrupt Evaluation Register (INTEVAL) ................................................................................ 69
6-4 Module Error Pending Register 1 (MERRPR1) ........................................................................ 70
6-5 Module Error Clear Register 1 (MERRCR1) ............................................................................ 70
6-6 Power Domain Transition Command Register (PTCMD) ............................................................. 71
6-7 Power Domain Transition Status Register (PTSTAT) ................................................................. 71
6-8 Power Domain Status 0 Register (PDSTAT0) .......................................................................... 72
6-9 Power Domain Control 0 Register (PDCTL0) .......................................................................... 73
6-10 Module Status n Register (MDSTAT n) .................................................................................. 74
6-11 Module Control n Register (MDCTL n) ................................................................................... 75
6 List of Figures SPRU978E – March 2008
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