DSP Subsystem Reference Guide

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Cache control
Memory protect
Bandwidth mgmt
L1P
RAM/
cache
256
Bandwidth mgmt
Memory protect
Cache control
256
L2
256
RAM/
Cache
ROM
256
Instruction fetch
file A file B
C64x+ CPU
256
Cache control
Memory protect
Bandwidth mgmt
L1D
128 128
8 x 32
IDMA
256
256
128
256
Power down
Interrupt
controller
CFG
MDMA SDMA
EMC
256
32
Chip
registers
64 64
RAM/
cache
Register Register
System
infrastructure
TMS320C64x+ CPU
• Protected mode operation: a two-level system of privileged program execution to support higher
capability operating systems and system features, such as memory protection
• Exceptions support for error detection and program redirection to provide robust code execution
• Hardware support for modulo loop operation to reduce code size
• Industry's first assembly optimizer for rapid development and improved parallelization
Figure 2-1. TMS320C64x+ Megamodule Block Diagram
SPRU978E – March 2008 TMS320C64x+ Megamodule 17
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