DDR2 Memory Controller User's Guide

List of Figures
1 Data Paths to DDR2 Memory Controller .................................................................................. 8
2 DDR2 Memory Controller Clock Block Diagram ......................................................................... 9
3 DDR2 Memory Controller Signals ........................................................................................ 11
4 Refresh Command ......................................................................................................... 13
5 DCAB Command ........................................................................................................... 14
6 DEAC Command ........................................................................................................... 15
7 ACTV Command ........................................................................................................... 16
8 DDR2 READ Command ................................................................................................... 17
9 DDR2 WRT Command .................................................................................................... 18
10 DDR2 MRS and EMRS Command ...................................................................................... 19
11 Byte Alignment .............................................................................................................. 20
12 Logical Address-to-DDR2 SDRAM Address Map ...................................................................... 24
13 DDR2 SDRAM Column, Row, and Bank Access ...................................................................... 25
14 DDR2 Memory Controller FIFO Block Diagram ........................................................................ 26
15 DDR2 Memory Controller Reset Block Diagram ....................................................................... 30
16 DDR2 Memory Controller Power Sleep Controller Diagram .......................................................... 34
17 Connecting DDR2 Memory Controller for 32-Bit Connection ......................................................... 37
18 Connecting DDR2 Memory Controller for 16-Bit Connection ......................................................... 37
19 SDRAM Status Register (SDRSTAT).................................................................................... 41
20 SDRAM Bank Configuration Register (SDBCR) ....................................................................... 42
21 SDRAM Refresh Control Register (SDRCR) ........................................................................... 44
22 SDRAM Timing Register (SDTIMR) ..................................................................................... 45
23 SDRAM Timing Register 2 (SDTIMR2).................................................................................. 46
24 Peripheral Bus Burst Priority Register (PBBPR) ....................................................................... 47
25 Interrupt Raw Register (IRR) ............................................................................................. 48
26 Interrupt Masked Register (IMR) ......................................................................................... 49
27 Interrupt Mask Set Register (IMSR) ..................................................................................... 50
28 Interrupt Mask Clear Register (IMCR) ................................................................................... 51
29 DDR PHY Control Register (DDRPHYCR) ............................................................................. 52
30 VTP IO Control Register (VTPIOCR) .................................................................................... 53
31 DDR VTP Register (DDRVTPR) ......................................................................................... 54
32 DDR VTP Enable Register (DDRVTPER) .............................................................................. 54
4 List of Figures SPRU986B – November 2007
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