DDR2 Memory Controller User's Guide

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Peripheral Architecture

Table 9. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM

SDBCR Bit Logical Address

(1)

IBANK PAGESIZE 31 30 29 28 27 26 25 24 23 22:16 15 14 13 12 11 10 9:2 1:0

0 0 - nrb=13 ncb=8

1 0 - nrb=13 nbb=1 ncb=8

2h 0 - nrb=13 nbb=2 ncb=8

3h 0 - nrb=13 nbb=3 ncb=8

0 1 - nrb=13 ncb=9

1 1 - nrb=13 nbb=1 ncb=9

2h 1 - nrb=13 nbb=2 ncb=9

3h 1 - nrb=13 nbb=3 ncb=9

0 2h - nrb=13 ncb=10

1 2h - nrb=13 nbb=1 ncb=10

2h 2h - nrb=13 nbb=2 ncb=10

3h 2h - nrb=13 nbb=3 ncb=10

0 3h - nrb=13 ncb=11

1 3h - nrb=13 nbb=1 ncb=11

2h 3h - nrb=13 nbb=2 ncb=11

3h 3h nrb=13 nbb=3 ncb=11

(1)

Legend: ncb = number of column address bits; nrb = number of row address bits; nbb = number of bank address bits.

Table 10. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM