DDR2 Memory Controller User's Guide

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2.6 Endianness Considerations
Peripheral Architecture
The DDR2 memory controller supports little-endian operating mode. This determines the order in which
data on the internal data bus is written to or read from devices that are not as wide as the internal data
bus. However, the DDR2 memory controller maintains the natural order of endian operations. That is, a
stream of data starting at any address N will always be accessed in the correct or incrementing data
order. The DDR2 memory controller will always access address N prior to N + 1 in any data width. Table 6
and Table 7 show operation of the DDR2 memory controller for both 16-bit and 32-bit external memory.
See the device-specific data manual for the memory widths that are supported.
Table 6. 16-Bit External Memory
Internal Data (64-Bit DDR_A[2:1] DDR_D[15:0]
0123 4567 89AB CDEFh 00 CDEFh
0123 4567 89AB CDEFh 01 89ABh
0123 4567 89AB CDEFh 10 4567h
0123 4567 89AB CDEFh 11 0123h
Table 7. 32-Bit External Memory
Internal Data (64-Bit) DDR_A[2] DDR_D[31:0]
0123 4567 89AB CDEFh 0 89AB CDEFh
0123 4567 89AB CDEFh 1 0123 4567h
SPRU986B – November 2007 DDR2 Memory Controller 21
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