Digital Media System-on-Chip (DMSoC) Product Preview

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PRODUCT PREVIEW
PLLDIV1(/2)
PLLDIV2(/4)
PLLDIV3(/3)
SYSCLK1
(ARMandMPEG/JPEG
Coprocessor)
SYSCLK2
(peripherals)
SYSCLK3
(VPBE)
1
0
PLL
0
1
CLKMODE
CLKIN
OSCIN
PLLEN
AUXCLK
(Peripherals,
CLKOUT1)
SYSCLKBP
(CLKOUT2)
Pre-DIV
(/8)
Post-DIV
(/2or/1)
PLLM
(programmable)
BPDIV(/3)
PLLDIV4
(/4or/2)
SYSCLK4
(VPSS)
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
Figure 3-3. PLLC1 Configuration In DM355
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