Digital Media System-on-Chip (DMSoC) Product Preview

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PRODUCT PREVIEW
3.5 Device Clocking
3.5.1 Overview
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
The DM355 requires one primary reference clock . The reference clock frequency may be generated
either by crystal input or by external oscillator. The reference clock is the clock at the pins named
MXI1/MXOI. The reference clock drives two separate PLL controllers (PLLC1 and PLLC2). PLLC1
generates the clocks required by the ARM, MPEG and JPEG co-processor, VPBE, VPSS, and
peripherals. PLL2 generates the clock required by the DDR PHY. A block diagram of DM355's clocking
architecture is shown in Figure 5-1 . The PLLs are described further in Section 3.6 .
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