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Digital Media System-on-Chip (DMSoC) Product Preview

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PRODUCT PREVIEW
3.2 ARM926EJ-S RISC CPU
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
– Image Pipe (IPIPE)
– H3A Engine (Hardware engine for computing Auto-focus, Auto white balance, and Auto exposure)
• Video Processing Back End (VPBE)
– On Screen Display (OSD)
– Video Encoder Engine (VENC)
Figure 3-1 shows the functional block diagram of the DM355 ARM Subsystem.
Figure 3-1. DM355 ARM Subsystem Block Diagram
The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of
ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all important. The
ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to
trade off between high performance and high code density. Specifically, the ARM926EJ-S processor
supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,
providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code
overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a
complete high performance subsystem, including:
• ARM926EJ -S integer core
• CP15 system control coprocessor
• Memory Management Unit (MMU)
• Separate instruction and data Caches
• Write buffer
• Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces
• Separate instruction and data AHB bus interfaces
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