Digital Media System-on-Chip (DMSoC) Product Preview

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PRODUCT PREVIEW
PCLK
2
1
3
4
4
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
5.9.1.4 VPFE Electrical Data/Timing
Table 5-17. Timing Requirements for VPFE PCLK Master/Slave Mode (see Figure 5-23 )
DM355-216 DM355-270
NO. UNIT
MIN MAX MIN MAX
1 t
c(PCLK)
Cycle time, PCLK
(1)
18.52 100 14.81 100 ns
2 t
w(PCLKH)
Pulse duration, PCLK high 5.7 5.7 ns
3 t
w(PCLKL)
Pulse duration, PCLK low 5.7 5.7 ns
4 t
t(PCLK)
Transition time, PCLK 3 3 ns
(1) The PCLK frequency must be less than or equal to half the VPSS clock frequency—i.e., PCLK ≤ SYSCLK4/2.
Figure 5-23. VPFE PCLK Timing
Table 5-18. Timing Requirements for VPFE (CCD) Slave Mode (see Figure 5-24 )
DM355
NO. UNIT
MIN MAX
5 t
su(CCDV-PCLK)
Setup time, CCD valid before PCLK edge 3 ns
6 t
h(PCLK-CCDV)
Hold time, CCD valid after PCLK edge 2 ns
7 t
su(HDV-PCLK)
Setup time, HD valid before PCLK edge 3 ns
8 t
h(PCLK-HDV)
Hold time, HD valid after PCLK edge 2 ns
9 t
su(VDV-PCLK)
Setup time, VD valid before PCLK edge 3 ns
10 t
h(PCLK-VDV)
Hold time, VD valid after PCLK edge 2 ns
11 t
su(C_WEV-PCLK)
Setup time, C_WE valid before PCLK edge 3 ns
12 t
h(PCLK-C_WEV)
Hold time, C_WE valid after PCLK edge 2 ns
13 t
su(C_FIELDV-PCLK)
Setup time, C_FIELD valid before PCLK edge 3 ns
14 t
h(PCLK-C_FIELDV)
Hold time, C_FIELD valid after PCLK edge 2 ns
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