Stereo System User Manual

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TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Figure 4-26 shows the bit layout of the CFGMCASP0 register and Table 4-19 contains a description of the
bits.
31 8
Reserved
7 3 2 0
Reserved AMUTEIN0
R/W, 0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Figure 4-26. CFGMCASP0 Register Bit Layout (0x4000 0018)
Table 4-19. CFGMCASP0 Register Bit Field Description (0x4000 0018)
RESET READ
BIT NO. NAME DESCRIPTION
VALUE WRITE
31:3 Reserved N/A N/A Reads are indeterminate. Only 0s should be written to these bits.
2:0 AMUTEIN0 0 R/W AMUTEIN0 Selects the source of the input to the McASP0 mute input.
000 = Select the input to be a constant '0'
001 = Select the input from AXR0[7]/SPI1_CLK
010 = Select the input from AXR0[8]/AXR1[5]/SPI1_SOMI
011 = Select the input from AXR0[9]/AXR1[4]/SPI1_SIMO
100 = Select the input from AHCLKR2
101 = Select the input from SPI0_SIMO
110 = Select the input from SPI0_SCS/I2C1_SCL
111 = Select the input from SPI0_ENA/I2C1_SDA
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