Stereo System User Manual

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TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Table 4-29. Additional
(1)
SPI Master Timings, 5-Pin Option
(2) (3)
NO. MIN MAX UNIT
Polarity = 0, Phase = 0,
0.5t
c(SPC)M
from SPIx_CLK falling
Max delay for slave to
Polarity = 0, Phase = 1,
deassert SPIx_ENA after
0
from SPIx_CLK falling
final SPIx_CLK edge to
18 t
d(SPC_ENA)M
ns
ensure master does not
Polarity = 1, Phase = 0,
0.5t
c(SPC)M
begin the next
from SPIx_CLK rising
transfer.
(4)
Polarity = 1, Phase = 1,
0
from SPIx_CLK rising
Polarity = 0, Phase = 0,
0.5t
c(SPC)M
from SPIx_CLK falling
Polarity = 0, Phase = 1,
Delay from final
0
from SPIx_CLK falling
SPIx_CLK edge to
20 t
d(SPC_SCS)M
ns
master deasserting
Polarity = 1, Phase = 0,
0.5t
c(SPC)M
SPIx_SCS
(5) (6)
from SPIx_CLK rising
Polarity = 1, Phase = 1,
0
from SPIx_CLK rising
Max delay for slave SPI to drive SPIx_ENA valid
21 t
d(SCSL_ENAL)M
after master asserts SPIx_SCS to delay the 0.5P ns
master from beginning the next transfer.
Polarity = 0, Phase = 0,
2P – 10
to SPIx_CLK rising
Polarity = 0, Phase = 1,
0.5t
c(SPC)M
+ 2P – 10
Delay from SPIx_SCS
to SPIx_CLK rising
22 t
d(SCS_SPC)M
active to first ns
Polarity = 1, Phase = 0,
SPIx_CLK
(7) (8) (9)
2P – 10
to SPIx_CLK falling
Polarity = 1, Phase = 1,
0.5t
c(SPC)M
+ 2P – 10
to SPIx_CLK falling
Polarity = 0, Phase = 0,
3P + 15
to SPIx_CLK rising
Polarity = 0, Phase = 1,
0.5t
c(SPC)M
+ 3P + 15
Delay from assertion of
to SPIx_CLK rising
23 t
d(ENA_SPC)M
SPIx_ENA low to first ns
Polarity = 1, Phase = 0,
SPIx_CLK edge.
(10)
3P + 15
to SPIx_CLK falling
Polarity = 1, Phase = 1,
0.5t
c(SPC)M
+ 3P + 15
to SPIx_CLK falling
(1) These parameters are in addition to the general timings for SPI master modes (Table 4-25 ).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPIx_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPIx_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPIx_ENA is asserted immediately such that the transmission is not delayed by SPIx_ENA.
(8) In the case where the master SPI is ready with new data before SPIx_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPIx_ENA was initially deasserted high and SPIx_CLK is delayed.
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