Interpolated Control (VIC) Port Reference Guide

Video Port Control Registers
2-21Video PortSPRU629
2.7.3 Video Port Interrupt Enable Register (VPIE)
The video port interrupt enable register (VPIE) enables sources of the video
port interrupt to the DSP. The VPIE is shown in Figure 2–5 and described in
Table 2–8.
Figure 2–5. Video Port Interrupt Enable Register (VPIE)
31 24
Reserved
R-0
23 22 21 20 19 18 17 16
LFDB
SFDB VINTB2 VINTB1 SERRB CCMPB COVRB GPIO
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
Reserved
DCNA DCMP DUND TICK STC Reserved
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0
76543210
LFDA
SFDA VINTA2 VINTA1 SERRA CCMPA COVRA VIE
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 2–8. Video Port Interrupt Enable Register (VPIE) Field Descriptions
Bit field
†
symval
†
Value Description
31–24 Reserved – 0 Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
23 LFDB Long field detected on channel B interrupt enable bit.
DISABLE 0 Interrupt is disabled.
ENABLE 1 Interrupt is enabled.
22
SFDB Short field detected on channel B interrupt enable bit.
DISABLE 0 Interrupt is disabled.
ENABLE 1 Interrupt is enabled.
21
VINTB2 Channel B field 2 vertical interrupt enable bit.
DISABLE 0 Interrupt is disabled.
ENABLE 1 Interrupt is enabled.
†
For CSL implementation, use the notation VP_VPIE_field_symval