Interpolated Control (VIC) Port Reference Guide

GPIO Registers
General Purpose I/O Operation5-20 SPRU629
Table 5–10. Video Port Pin Interrupt Enable Register (PIEN) Field Descriptions
Bit field
†
symval
†
Value Description
31–23 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
22 PIEN22 PIEN22 bit enables the interrupt on the VCTL3 pin.
VCTL3LO 0 Interrupt is disabled.
VCTL3HI 1 Pin enables the interrupt.
21
PIEN21 PIEN21 bit enables the interrupt on the VCTL2 pin.
VCTL2LO 0 Interrupt is disabled.
VCTL2HI 1 Pin enables the interrupt.
20
PIEN20 PIEN20 bit enables the interrupt on the VCTL1 pin.
VCTL1LO 0 Interrupt is disabled.
VCTL1HI 1 Pin enables the interrupt.
19–0
PIEN[19–0] PIEN[19–0] bits enable the interrupt on the corresponding
VDATA[n] pin.
VDATAnLO 0 Interrupt is disabled.
VDATAnHI 1 Pin enables the interrupt.
†
For CSL implementation, use the notation VP_PIEN_PIENn_symval