Interpolated Control (VIC) Port Reference Guide

GPIO Registers
5-17General Purpose I/O OperationSPRU629
5.1.8 Video Port Pin Data Clear Register (PDCLR)
The video port pin data clear register (PDCLR) is shown in Figure 5–8 and
described in Table 5–9. PDCLR is an alias of the video port pin data output reg-
ister (PDOUT) for writes only and provides an alternate means of driving GPIO
outputs low. Writing a 1 to a bit of PDCLR clears the corresponding bit in
PDOUT. Writing a 0 has no effect. Register reads return all 0s.
Figure 5–8. Video Port Pin Data Clear Register (PDCLR)
31 24
Reserved
R-0
23 22 21 20 19 18 17 16
Reserved PDCLR22 PDCLR21 PDCLR20 PDCLR19 PDCLR18 PDCLR17 PDCLR16
R-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
15 14 13 12 11 10 9 8
PDCLR15 PDCLR14 PDCLR13 PDCLR12 PDCLR11 PDCLR10 PDCLR9 PDCLR8
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
76543210
PDCLR7 PDCLR6 PDCLR5 PDCLR4 PDCLR3 PDCLR2 PDCLR1 PDCLR0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
Legend: R = Read only; W = Write only; -n = value after reset