Interpolated Control (VIC) Port Reference Guide

GPIO Registers
General Purpose I/O Operation5-16 SPRU629
Table 5–8. Video Port Pin Data Set Register (PDSET) Field Descriptions
Bit field
†
symval
†
Value Description
31–23 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
22 PDSET22 Allows PDOUT22 bit to be set to a logic high without affect-
ing other I/O pins controlled by the same port.
NONE 0 No effect.
VCTL3HI 1 Sets PDOUT22 (VCTL3) bit to 1.
21
PDSET21 Allows PDOUT21 bit to be set to a logic high without affect-
ing other I/O pins controlled by the same port.
NONE 0 No effect.
VCTL2HI 1 Sets PDOUT21 (VCTL2) bit to 1.
20
PDSET20 Allows PDOUT20 bit to be set to a logic high without affect-
ing other I/O pins controlled by the same port.
NONE 0 No effect.
VCTL1HI 1 Sets PDOUT20 (VCTL1) bit to 1.
19–0
PDSET[19–0] Allows PDOUT[19–0] bit to be set to a logic high without
affecting other I/O pins controlled by the same port.
NONE 0 No effect.
VDATAnHI 1 Sets PDOUT[n] (VDATA[n]) bit to 1.
†
For CSL implementation, use the notation VP_PDSET_PDSETn_symval