Interpolated Control (VIC) Port Reference Guide

Video Display Registers
4-81Video Display PortSPRU629
4.12.19 Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2)
The video display field 2 vertical synchronization start register (VDVSYNS2)
controls the start of vertical synchronization in field 2. The VDVSYNS2 is
shown in Figure 4–57 and described in Table 4–24.
Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.
The VSYNC signal is asserted whenever the frame line counter (FLCOUNT)
is equal to VSYNCYSTART2 and the frame pixel counter (FPCOUNT) is equal
to VSYNCXSTART2.
Figure 4–57. Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2)
31 28 27 16
Reserved
VSYNCYSTART2
R-0 R/W-0
15 12 11 0
Reserved
VSYNCXSTART2
R-0 R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4–24. Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2)
Field Descriptions
Bit field
†
symval
†
Value Description
31–28 Reserved – 0 Reserved. The reserved bit location is always read as
0. A value written to this field has no effect.
27–16 VSYNCYSTART2 OF(value) 0–FFFh Specifies the line where VSYNC is asserted for
field 2.
15–12 Reserved – 0 Reserved. The reserved bit location is always read as
0. A value written to this field has no effect.
11–0 VSYNCXSTART2 OF(value) 0–FFFh Specifies the pixel where VSYNC is asserted in
field 2.
†
For CSL implementation, use the notation VP_VDVSYNS2_field_symval