Interpolated Control (VIC) Port Reference Guide

Video Display Registers
Video Display Port4-78 SPRU629
4.12.16 Video Display Horizontal Synchronization Register (VDHSYNC)
The video display horizontal synchronization register (VDHSYNC) controls
the timing of the horizontal synchronization signal. The VDHSYNC is shown
in Figure 4–54 and described in Table 4–21.
Generation of the horizontal synchronization is shown in Figure 4–5,
page 4-6. The HSYNC signal is asserted to indicate the start of the horizontal
sync pulse whenever the frame pixel counter (FPCOUNT) is equal to HSYNC-
START. The HSYNC signal is deasserted to indicate the end of the horizontal
sync pulse whenever FPCOUNT = HSYNCSTOP.
Figure 4–54. Video Display Horizontal Synchronization Register (VDHSYNC)
31 28 27 16
Reserved
HSYNCSTOP
R-0 R/W-0
15 12 11 0
Reserved
HSYNCSTART
R-0 R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4–21. Video Display Horizontal Synchronization Register (VDHSYNC)
Field Descriptions
Bit field
†
symval
†
Value Description
31–28 Reserved – 0 Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.
27–16 HSYNCSTOP OF(value) 0–FFFh Specifies the pixel where HSYNC is deasserted.
15–12 Reserved – 0 Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.
11–0 HSYNCSTART OF(value) 0–FFFh Specifies the pixel where HSYNC is asserted.
†
For CSL implementation, use the notation VP_VDHSYNC_field_symval