Interpolated Control (VIC) Port Reference Guide

Video Display Registers
Video Display Port4-62 SPRU629
Table 4–9. Video Display Horizontal Blanking Register (VDHBLNK) Field Descriptions
Description
Bit field
†
symval
†
Value
BT.656 and Y/C Mode
Raw Data Mode
31–28 Reserved – 0 Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.
27–16 HBLNKSTOP OF(value) 0–FFFh Location of SAV code and
HBLNK inactive edge
within the line. HBLNK
inactive edge may be
optionally delayed by
4 VCLKs.
Ending pixel (FPCOUNT)
of blanking video area
(HBLNK inactive) within
the line.
15 HBDLA Horizontal blanking delay enable bit.
NONE 0 Horizontal blanking delay
is disabled.
Not used.
DELAY 1 HBLNK inactive edge is
delayed by 4 VCLKs.
Not used.
14–12 Reserved – 0 Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.
11–0 HBLNKSTART OF(value) 0–FFFh Location of EAV code and
HBLNK active edge within
the line.
Starting pixel (FPCOUNT)
of blanking video area
(HBLNK active) within the
line.
†
For CSL implementation, use the notation VP_VDHBLNK_field_symval
4.12.5 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)
The video display field 1 vertical blanking start register (VDVBLKS1) controls
the start of vertical blanking in field 1. The VDVBLKS1 is shown in Figure 4–43
and described in Table 4–10.
In raw data mode, VBLNK is asserted whenever the frame line counter
(FLCOUNT) is equal to VBLNKYSTART1 and the frame pixel counter
(FPCOUNT) is equal to VBLNKXSTART1 (this is shown in Figure 4–6,
page 4-7).
In BT.656 and Y/C mode, VBLNK is asserted whenever
FLCOUNT = VBLNKYSTART1 and FPCOUNT = VBLNKXSTART1. This
VBLNK output control is completely independent of the timing control codes.
The V bit in the EAV/SAV codes for field 1 is controlled by the VDVBIT1 register.