Interpolated Control (VIC) Port Reference Guide

Display Timing Examples
Video Display Port4-46 SPRU629
Figure 4–38. Y/C Progressive Display Vertical Timing Example
5
FLCOUNT
750
716
716
ILCOUNT
Field 1 Blanking
Field 1 Blanking
Field 1 Active
4
3
2
1
716
716
716
716
25
26
27
716
716
716
745
746
747
748
749
716
716
716
716
716
28
29
Field 1 Image
744
1
2
716
715
VF
01
01
01
01
01
01
01
00
00
00
01
01
01
01
716
EAV
00
00
00
00
00
6 716 01
750 716 01
Active
Horizontal
Output
Blanking Value
Blanking Value
Blanking Value
Blanking Value
Blanking Value
Blanking Value
Blanking Value
Blanking Value
Default Value
§
Default Value
§
Default Value
§
FIFO Data
FIFO Data
FIFO Data
FIFO Data
Default Value
§
Blanking Value
Blanking Value
Blanking Value
Blanking Value
Blanking Value
1
716
716
01
01
Blanking Value
Blanking Value
FLD VBLNK
†
§
VSYNC
†
§
IMGVOFF1 = 3 VBLNKXSTART1 = 1280 VSYNCXSTART1 = 1280 FLD1XSTART = n/a
IMGVSIZE1 = 716 VBLNKYSTART1 = 746 VSYNCYSTART1 = 1 FLD1YSTART = 1
IMGVOFF2 = n/a VBLNKXSTOP1 = 1280 VSYNCXSTOP1 = 1280 FLD2XSTART = n/a
IMGVSIZE2 = n/a VBLNKYSTOP1 = 26 VSYNCYSTOP1 = 6 FLD2YSTART = > 750
FRMHEIGHT = 750 VBLNKXSTART2 = n/a VSYNCXSTART2 = n/a
VBITSET1 = 746 VBLNKYSTART2 = > 750 VSYNCYSTART2 = > 750 FBITSET = 1
VBITCLR1 = 26 VBLNKXSTOP2 = n/a VSYNCXSTOP2 = n/a FBITCLR = > 750
VBITSET2 = n/a VBLNKYSTOP2 = > 750 VSYNCYSTOP2 = > 750
VBITCLR2 = n/a
†
Assumes VCT2P bit in VPCTL is set to 1 (active-low output). VSYNC output when VCTL2S bit in VDCTL is set to 00, VBLNK
output when VCTL2S bit is set 01.
§
If DVEN bit in VDCTL is set to 1; otherwise, blanking value is output