Interpolated Control (VIC) Port Reference Guide

Display Timing Examples
4-40 Video Display Port
SPRU629
Figure 4–35. Raw Interlaced Display Horizontal Timing Example
FLCOUNT
VDOUT[19–0] §
VCLKOUT
VCLKIN
IPCOUNT
VCTL1 (HBLNK)
†
§
VCTL1 (HSYNC)
†
§
Blanking
n – 1 n + 1n
Raw0
(R0)
Raw1
(G0)
Raw2
(B0)
Raw3
(R1)
Raw4
(G1)
Raw5
(B1)
Raw2108
(B702)
Raw2109
(R703)
Raw2110
(G703)
Raw2111
(B703)
FPCOUNT
720 721 735 736 799 800 857 0 1 7 8 9 711 712 719 720 721
414 2112
One Line Next Line
703 0 1 703 703 703 703 703
Active Video
Display Image
703 703 703 703 703 703 703 703 703
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FRMWIDTH = 858 IMGHOFF1 = 8 HSYNCSTART = 736
HBLNKSTART = 720 IMGHSIZE1 = 704 HSYNCSTOP = 800
HBLNKSTOP = 0 IMGHOFF2 = 8
IMGHSIZE2 = 704 INCPIX = 3
†
Assumes VCT1P bit in VPCTL is set to 1 (active-low output). HSYNC output when VCTL1S bit in VDCTL is set to 00,
HBLNK output when VCTL1S bit is set 01.
§
Diagram assumes a two VCLK pipeline delay between internal counters and output signals.