User's Guide

Watchdog Timer Mode

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The PRDHI, PRDLO, TCR, and WDTCR registers must be configured before the watchdog timer enters

the active state. The WDEN bit must be set to 1 before writing DA7Eh to the WDKEY bits in the pre-active

state. Every time the watchdog timer is serviced by the correct WDKEY sequence, the watchdog timer

counter is automatically reset.

NOTE: Before the watchdog timer enters the active state, the timer output signal is never asserted.

Only the timer interrupt is asserted when the timer finishes counting up. In this case, the

timer interrupt can be used to:

• Indicate that the watchdog timer is counting but is not in the active state.

• Generate a periodic interrupt, without having to service the watchdog timer.

The watchdog timer can always be disabled before entering the active state.

4.4 Watchdog Timer Register Write Protection

Once the watchdog timer enters the pre-active state, writes to registers CNTHI, CNTLO, PRDHI, PRDLO,

TCR, and WDTCR (except for the WDKEY bits) will have no effect. Writes to WDEN when the watchdog

timer is in the timeout state have no effect.

The value 0xA5C6 or 0xDA7E must be written to the WDKEY bits depending on the current state (see

Figure 12). After the watchdog timer has entered the initial state, clearing the TIMLORS and TIMHIRS bits

is prohibited.

C6472/TCI648x 64-Bit Timer SPRU818B–December 2005–Revised September 2010

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