User's Guide

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Timer Operation

3.9.3 Timer Count = 0, Timer Period = 0, Prescale Count = 0, and Prescale Period = 0

Consider a timer that has a prescaler:

• The combination timer in the 32-bit dual timers chained mode.

• TIMHI in the 32-bit dual timer configuration (unchained mode).

In the special case when timer count = 0, timer period = 0, prescale count = 0, and prescale period = 0,

the timer operates in the same manner as a non-prescaled timer with timer count = 0 and timer period = 0

(see Section 3.9.2).

3.9.4 Timer Counter Overflow

Timer counter overflow can happen when the timer counter register is set to a value greater than the value

in the timer period register. The counter reaches its maximum value (FFFF FFFFh or FFFF FFFF FFFF

FFFFh), rolls over to 0, and continues counting until it reaches the timer period. An example is shown in

Figure 9.

Figure 9. 32-Bit Timer Counter Overflow Example

3.9.5 Writing to Registers of an Active Timer

Writes from the configuration bus to the timer registers are not allowed when the timer is active, except for

stopping or resetting the timers. In the 64-bit and dual 32-bit timer modes, registers that are protected by

hardware include CNTLO, CNTHI, PRDLO, PRDHI, TGCR (except the TIMLORS and TIMHIRS bits), and

TCR (except the ENAMODE bits).

3.9.6 Small Timer Period Value in Pulse Mode

Small timer periods in pulse mode (CP = 0) can cause TSTAT to remain high when ENAMODE is not 0.

This condition can occur when PRD . PWID + 1.

3.9.7 Reading the Counter Registers

Table 7 summarizes how to read the counter registers. When reading the timer counter in 64-bit GP timer

mode, the CPU must read the first 32-bit word from the CNTLO registers. When this occurs, the timer

takes a snapshot of the CNTHI register and copies it into a shadow register CNTHIS. Note that reading

CNTHI instead of CNTLO will not cause the timer to take a snap shot of the timer counters and copy them

into the shadow registers.

Table 7. Reading Counter Registers

Timer Mode CPU

64-bit timer Read CNTLO → Read CNTLO

Copy CNTHI to CNTHIS

Read CNTHI → Read from CNTHIS

32-bit timer Read CNTLO → Read CNTLO

Read CNTHI → Read CNTHI

SPRU818B–December 2005–Revised September 2010 C6472/TCI648x 64-Bit Timer

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