Incor User's Guide Ethernet Media Access Controller TMS320C645x DSP

53 Receive Buffer Offset Register (RXBUFFEROFFSET) .............................................................. 109
54 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) .............................. 110
55 Receive Channel n Flow Control Threshold Register (RX nFLOWTHRESH) ..................................... 111
56 Receive Channel n Free Buffer Count Register (RX nFREEBUFFER) ............................................ 112
57 MAC Control Register (MACCONTROL) .............................................................................. 113
58 MAC Status Register (MACSTATUS) .................................................................................. 115
59 Emulation Control Register (EMCONTROL) .......................................................................... 117
60 FIFO Control Register (FIFOCONTROL) .............................................................................. 118
61 MAC Configuration Register (MACCONFIG) ......................................................................... 119
62 Soft Reset Register (SOFTRESET) .................................................................................... 120
63 MAC Source Address Low Bytes Register (MACSRCADDRLO)................................................... 121
64 MAC Source Address High Bytes Register (MACSRCADDRHI) ................................................... 122
65 MAC Hash Address Register 1 (MACHASH1) ........................................................................ 123
66 MAC Hash Address Register 2 (MACHASH2) ........................................................................ 124
67 Back Off Random Number Generator Test Register (BOFFTEST) ................................................ 125
68 Transmit Pacing Algorithm Test Register (TPACETEST) ........................................................... 126
69 Receive Pause Timer Register (RXPAUSE) .......................................................................... 127
70 Transmit Pause Timer Register (TXPAUSE) .......................................................................... 128
71 MAC Address Low Bytes Register (MACADDRLO) .................................................................. 129
72 MAC Address High Bytes Register (MACADDRHI) .................................................................. 130
73 MAC Index Register (MACINDEX) ..................................................................................... 131
74 Transmit Channel n DMA Head Descriptor Pointer Register (TX nHDP) .......................................... 132
75 Receive Channel n DMA Head Descriptor Pointer Register (RX nHDP) .......................................... 133
76 Transmit Channel n Completion Pointer Register (TX nCP) ......................................................... 134
77 Receive Channel n Completion Pointer Register (RX nCP) ......................................................... 135
78 Statistics Register ......................................................................................................... 136
SPRU975B – August 2006 List of Figures 7
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