Incor User's Guide Ethernet Media Access Controller TMS320C645x DSP

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5.49 Receive Channel 0-7 Completion Pointer Register (RX nCP)
EMAC Port Registers
The receive channel 0-7 completion pointer register (RX nCP) is shown in Figure 77 and described in
Table 77 .
Figure 77. Receive Channel n Completion Pointer Register (RX nCP)
31 16
RX nCP
R/W-x
15 0
RX nCP
R/W-x
LEGEND: R/W = Read/Write; - n = value after reset
Table 77. Receive Channel n Completion Pointer Register (RX nCP) Field Descriptions
Bit Field Value Description
31-0 RX nCP Receive channel n completion pointer register is written by the host with the buffer descriptor
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be de-asserted.
SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 135
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