Incor User's Guide Ethernet Media Access Controller TMS320C645x DSP

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5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
EMAC Port Registers
The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Figure 48 and described in
Table 48 .
Figure 48. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
31 16
Reserved
R-0
15 2 1 0
Reserved HOST STAT
MASK MASK
R-0 R/WC-0 R/WC-0
LEGEND: R = Read only; R/W = Read/Write; R/WC = Read/Write 1 to clear; - n = value after reset
Table 48. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 HOSTMASK Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
0 STATMASK Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 103
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