User's Manual

6.11 TCP2 Input Configuration Register 8 (TCPIC8)
www.ti.com Registers
The TCP2 input configuration register 8 (TCPIC8) is shown in Figure 41 and described in Table 15 .
TCPIC8 sets the tail bits used by the TCP.
Figure 41. TCP2 Input Configuration Register 8 (TCPIC8)
31 18 17 0
Reserved TAIL3
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 15. TCP2 Input Configuration Register 8 (TCPIC8) Field Descriptions
Bit Field Value Description
31-18 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has
no effect.
17-0 TAIL3 0-FFFF FFFFh Tail bit. Values must be set as in the following list.
• CDMA-2000 Tail Symbol Pattern for Code Rate 1/5
tail+2 tail+1 tail+0
p11 p11 p11
• CDMA-2000 Tail Symbol Pattern for Code Rate 1/4
tail+2 tail+1 tail+0
p11 p11 p11
• CDMA-2000 Tail Symbol Pattern for Code Rate 1/3
tail+2 tail+1 tail+0
0 0 0
• CDMA-2000 Tail Symbol Pattern for Code Rate 1/5 or 1/4
tail+2 tail+1 tail+0
p11 p11 p11
• CDMA-2000 Tail Symbol Pattern for Code Rate 1/3, 1/2, or 3/4
tail+2 tail+1 tail+0
SPRUGK1 – March 2009 TMS320C6457 Turbo-Decoder Coprocessor 2 35
Submit Documentation Feedback