Network Router User Manual

01 01

HPIA Write HPID+ Writes

HCNTL[1:0]

HD[31:0]

HRDY

HR/W

Internal

HSTRB

HCS

HPIA Write HPID+ Writes

HD[31:0]

HRDY

Internal

HSTRB

HCS

HCNTL[1:0]

HR/W

HPI Operation

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Figure 24. HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode

(Case 2: Autoincrementing Selected, FIFO Empty Before Write)

A HCS may be brought high during strobe cycles. However, note that HRDY is gated by HCS.

Figure 25 shows an HPIA (HCNTL[1:0] = 10b) write access when the write FIFO is not empty, followed by

several autoincrementing HPID (HCNTL[1:0] = 01b) write accesses. Note that HRDY is active twice for the

HPIA access. This occurs because the FIFO is not empty and the data in the FIFO must first be written to

memory. This results in an HRDY assertion immediately after the falling edge of the datastrobe (HSTRB).

When a write request to memory has been made that will empty the internal FIFO, the HPIA write

operation can complete with the rising edge of HSTRB. The second HRDY assertion is for the write to the

HPIA register. HRDY is not active for the HPID accesses.

Figure 25. HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode

(Case 3: Autoincrementing Selected, FIFO Not Empty Before Write)

A HCS may be brought high during strobe cycles. However, note that HRDY is gated by HCS.

Host Port Interface (HPI) SPRUGK7A–March 2009–Revised July 2010