Network Router User Manual

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1st halfword 2nd halfword

0000

Internal

HD[15:0]

HRDY

HHWIL

HR/W

HCNTL[1:0]

HCS

HSTRB

10 10 11 11

1st halfword 2nd halfword2nd halfword1st halfword

Internal

HSTRB

HD[15:0]

HRDY

HHWIL

HR/W

HCNTL[1:0]

HCS

HPIA write HPID write

10 10 01 01 01

1st halfword2nd halfword1st halfword2nd halfword1st halfword

Internal

HSTRB

HD[15:0]

HRDY

HHWIL

HR/W

HCNTL[1:0]

HCS

HPIA write HPID+ writes

HPI Operation

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3.9.2 HRDY Behavior During 16-Bit Multiplexed Write Operations

Figure 15 shows an HPIC (HCNTL[1:0] = 00b) write cycle during 16-bit multiplexed HPI operation. An

HPIC write cycle does not cause HRDY to go high.

Figure 15. HRDY Behavior During an HPIC Write Cycle in the 16-Bit Multiplexed Mode

Figure 16 includes a HPID write cycle without autoincrementing in the 16-bit multiplexed mode. The host

writes the memory address while HCNTL[1:0] = 10b and writes the data while HCNTL[1:0] = 11b. During

the HPID write cycle, HRDY goes high only for the second halfword access.

Figure 16. HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode

(Case 1: No Autoincrementing)

Figure 17 shows autoincrement HPID write cycles in the 16-bit multiplexed mode when the write FIFO is

empty prior to the HPIA write. The host writes the memory address while HCNTL[1:0] = 10b and writes the

data while HCNTL[1:0] = 01b. HRDY does not go high during any of the HPID write cycles.

Figure 17. HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode

(Case 2: Autoincrementing Selected, FIFO Empty Before Write)

Figure 18 shows a case similar to that of Figure 17. However, in Figure 18, the write FIFO is not empty

when the HPIA access is made. HRDY goes high twice for the first halfword access of the HPIA write

cycle. The first HRDY high period is due to the non-empty FIFO. The data currently in the FIFO must first

be written to the memory. This results in HRDY going high immediately after the falling edge of the data

strobe (HSTRB). The second and third HRDY high periods occur for the writes to the HPIA. HRDY

remains low for the HPID accesses.

Host Port Interface (HPI) SPRUGK7A–March 2009–Revised July 2010